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ISQED
2007
IEEE

A Design Methodology for Matching Improvement in Bandgap References

10 years 6 months ago
A Design Methodology for Matching Improvement in Bandgap References
Errors caused by tolerance variations and mismatches among components severely degrade the performance of integrated circuits. These random effects in process parameters significantly impact manufacture costs by decreasing yield and so by including extra-circuits for adjustment. In this paper we propose a design methodology based on the Pelgrom’s MOS transistormismatching model devices. Our main objective is to calculate the size of each component considering their relation between area and mismatching. Therefore, in order to validate our proposal methodology, we used as a design target a bandgap reference circuit fabricated in 0.35µm CMOS technology. Its temperature coefficient attains an average value of 40ppm/ºC and an average output voltage of 1,20714V. It also includes a straightforward 4-bits trim circuit to achieve more process independence variation. As a result of our methodology, the considerable area of 400x350µm2 was occupied due to our matching design requirements.
Juan Pablo Martinez Brito, Hamilton Klimach, Sergi
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where ISQED
Authors Juan Pablo Martinez Brito, Hamilton Klimach, Sergio Bampi
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