Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

6

ASPDAC
2008
ACM

favoriteEmaildiscussreport

72views Hardware» more ASPDAC 2008»

Design rule optimization of regular layout for leakage reduction in nanoscale design

13 years 6 months ago

Design rule optimization of regular layout for leakage reduction in nanoscale design

Download www.cecs.uci.edu

Anupama R. Subramaniam, Ritu Singhal, Chi-Chao Wan

Real-time Traffic

ASPDAC 2008 | Hardware |

claim paper

Related Content

» Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems

» AreaEfficient Selective MultiThreshold CMOS Design Methodology for Standby Leakage Power R...

» Variabilityaware optimization of nanoCMOS Active Pixel Sensors using design and analysis o...

» Area optimization for leakage reduction and thermal stability in nanometer scale technolog...

» Detailed placement for leakage reduction using systematic throughpitch variation

» Selective gatelength biasing for costeffective runtime leakage control

» IO Clustering in Design Cost and Performance Optimization for FlipChip Design

» A Scalable Algorithmic Framework for RowBased PowerGating

» Architecture and circuit techniques for lowthroughput energyconstrained systems across tec...

Post Info
More Details (n/a)

Added	12 Oct 2010
Updated	12 Oct 2010
Type	Conference
Year	2008
Where	ASPDAC
Authors	Anupama R. Subramaniam, Ritu Singhal, Chi-Chao Wang, Yu Cao

Comments (0)