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DATE
2009
IEEE

Design as you see FIT: System-level soft error analysis of sequential circuits

9 years 7 months ago
Design as you see FIT: System-level soft error analysis of sequential circuits
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardening have been proposed to synthesize circuits that are tolerant to soft errors. However, each such technique has associated overheads of power, area, and performance. In this paper, we present a new methodology to compute the failures in time (FIT) rate of a sequential circuit where the failures are at the system-level. System-level failures are detected by monitors derived from functional specifications. Our approach includes efficient methods to compute the FIT rate of combinational circuits (CFIT), incorporating effects of logical, timing, and electrical masking. The contribution of circuit components to the FIT rate of the overall circuit can be computed from the CFIT and probabilities of system-level failure due to soft errors in those elements. Designers can use this information to perform Pareto-optim...
Daniel Holcomb, Wenchao Li, Sanjit A. Seshia
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where DATE
Authors Daniel Holcomb, Wenchao Li, Sanjit A. Seshia
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