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DSD
2008
IEEE

Digital Systems Architectures Based on On-line Checkers

8 years 9 months ago
Digital Systems Architectures Based on On-line Checkers
In this paper, a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of communication protocols, counters, decoders, registers, comparators, etc. It is also demonstrated how a checker for more complex structures can be developed. We describe the possibilities of utilizing this approach in the design of Fault Tolerant Systems (FTS). Experimental results in terms of FPGA resources needed to synthesize different types of checkers are presented.
Martin Straka, Zdenek Kotásek, Jan Winter
Added 29 May 2010
Updated 29 May 2010
Type Conference
Year 2008
Where DSD
Authors Martin Straka, Zdenek Kotásek, Jan Winter
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