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HIPC
2007
Springer

Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors

10 years 1 months ago
Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors
Traditional directory-based cache coherence protocols suffer from long-latency cache misses as a consequence of the indirection introduced by the home node, which must be accessed on every cache miss before any coherence action can be performed. In this work we present a new protocol that moves the role of storing up-to-date coherence information (and thus ensuring totally ordered accesses) from the home node to one of the sharing caches. Our protocol allows most cache misses to be directly solved from the corresponding remote caches, without requiring the intervention of the home node. In this way, cache miss latencies are reduced. Detailed simulations show that this protocol leads to improvements in total execution time of 8% on average over a highly optimized MOESI directory-based protocol.
Alberto Ros, Manuel E. Acacio, José M. Garc
Added 07 Jun 2010
Updated 07 Jun 2010
Type Conference
Year 2007
Where HIPC
Authors Alberto Ros, Manuel E. Acacio, José M. García
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