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CHES
2005
Springer

DPA Leakage Models for CMOS Logic Circuits

9 years 7 months ago
DPA Leakage Models for CMOS Logic Circuits
In this paper, we propose new models for directly evaluating DPA leakage from logic information in CMOS circuits. These models are based on the transition probability for each gate, and are naturally applicable to various actual devices for simulating power analysis. We also report the effectiveness of the previously known enhanced DPA on our model. Furthermore, we demonstrate the weakness of previously known hardware countermeasures for both our model and FPGA and suggest secure conditions for the hardware countermeasure.
Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa
Added 26 Jun 2010
Updated 26 Jun 2010
Type Conference
Year 2005
Where CHES
Authors Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa
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