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1996
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DSP Processor/Compiler Co-Design: A Quantitative Approach

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DSP Processor/Compiler Co-Design: A Quantitative Approach
In the paper the problem of processor/compiler codesign for digital signal processing and embedded SYstems is discussed. The main principle we follow is the top-down approach characterized by extensive simulation and quantitative performance evaluation of processor and compiler. Although well established in the design of state-of-the-art general purpose processors and compilers, this approach is rarely followed by leading producers of signal and embedded processors. A s a consequence, the matching between the processor and the compiler is low. In the paper we focus on three main components of our exploration environment - benchmarking methodology (DSPstone), fast processor simulation (SuperSim), and machine description (LISA). Most of the paper is devoted to the technique of compiled processor simulation. The speedup obtained allows an exploration of a much larger design space than it was possible with standard processor simulators.
Vojin Zivojnovic, Stefan Pees, C. Schälger, M
Added 07 Aug 2010
Updated 07 Aug 2010
Type Conference
Year 1996
Where ISSS
Authors Vojin Zivojnovic, Stefan Pees, C. Schälger, Markus Willems, R. Schoenen, Heinrich Meyr
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