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2004
ACM

A dual-core 64b ultraSPARC microprocessor for dense server applications

9 years 3 months ago
A dual-core 64b ultraSPARC microprocessor for dense server applications
A processor core, previously implemented in a 0.25m Al process, is redesigned for a 0.13m Cu process to create a dualcore processor with 1MB integrated L2 cache, offering an efficient performance/power ratio for compute-dense server applications. Deep submicron circuit design challenges, including negative bias temperature instability (NBTI), leakage and coupling noise, and L2 cache implementation are discussed. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles
Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petri
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2004
Where DAC
Authors Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Su, Ana Sonia Leon
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