A dual-MST approach for clock network synthesis

9 years 11 months ago
A dual-MST approach for clock network synthesis
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Voltage and Temperature) variations contribute a lot to its behavior. Previous works mainly focused on skew and wirelength minimization. It may lead to negative influence towards these process variation factors. In this paper, a novel clock network synthesizer is proposed and several algorithms are introduced for performance improvement. A dual-MST (DMST) geometric matching approach is proposed for topology construction. It can help balancing the tree structure to reduce the variation effect. A recursive buffer insertion technique and a blockage handling method are also presented, and they are developed for proper distribution of buffers and saving of capacitance. Experimental results show that our matching approach is better than the traditional methods, and in particular our synthesizer has better performance co...
Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangel
Added 10 Feb 2011
Updated 10 Feb 2011
Type Journal
Year 2010
Authors Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangeline F. Y. Young
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