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2008
ACM

DVFS in loop accelerators using BLADES

9 years 11 months ago
DVFS in loop accelerators using BLADES
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-to-market and reduced non-recurring engineering costs, automatic systems that can rapidly generate hardware bearing both power and performance in mind are extremely attractive. This paper proposes the BLADES (Better-than-worst-case Loop Accelerator Design) system for automatically designing self-tuning hardware accelerators that dynamically select their best operating frequency and voltage based on environmental conditions, silicon variation, and input data characteristics. Errors in operation are detected by Razor flip-flops, and recovery is initiated. The architecture efficiently supports detection, rollback, and recovery to provide a highly adaptable and configurable loop accelerator. The overhead of deploying Razor flip-flops is significantly reduced by automatically chaining primitive computation operatio...
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott
Added 12 Nov 2009
Updated 12 Nov 2009
Type Conference
Year 2008
Where DAC
Authors Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David Bull
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