Dynamic hardware plugins in an FPGA with partial run-time reconfiguration

Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet processing circuits on this platform are implemented as Dynamic Hardware Plugin (DHP) modules that fit within a specific region of an FPGA device. The PARBIT tool has been developed to transform and restructure bitfiles created by standard computer aided design tools into partial bitsteams that program DHPs. The methodology allows the platform to hot-swap application-specific DHP modules without disturbing the operation of the rest of the system. Keywords FPGA, partial RTR, reconfiguration, hardware, modularity, network, routing, packet, Internet, IP, platform computing Categories and Subject Descriptors B.7.2 [Hardware]: Circuits--Design Aids; B.7.1 [Hardware]: Circuits--VLSI ; B.4.3 [Hardware]: Input/Output and Data Communications--Interconnections (Subsystems); C.2.1 [Computer Systems Organization]: Computer...

• Type: Conference
• Year: 2002
• Where: DAC
• Authors: Edson L. Horta, John W. Lockwood, David E. Taylor, David Parlour
• Keywords: DAC 2002, Design Automation, Dynamic Hardware Plugin, Hot-swap Application-specific Dhp, Partial Run-time Reconfiguration