Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors

Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-delay-constrained process technologies. As increasing transistor counts allow an increase in the number of clusters, thereby allowing more aggressive use of instructionlevel parallelism (ILP), the inter-cluster communication increases as data values get spread across a wider area. As a result of the emergence of this trade-off between communication and parallelism, a subset of the total on-chip clusters is optimal for performance. To match the hardware to the application’s needs, we use a robust algorithm to dynamically tune the clustered architecture. The algorithm, which is based on program metrics gathered at periodic intervals, achieves an 11% performance improvement on average over the best statically defined architecture. We also show that the use of additional hardware and reconfiguration at basic b...

• Type: Conference
• Year: 2003
• Where: ISCA
• Authors: Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
• Keywords: Hardware, Inter-cluster Communication Increases, ISCA 2003, Monolithic Superscalar Designs, Total On-chip Clusters