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12

HPCN
1998
Springer

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Dynamically Trace Scheduled VLIW Architectures

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Dynamically Trace Scheduled VLIW Architectures

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This paper presents a new architecture organisation, the dynamically trace scheduled VLIW (DTSVLIW), that can be used to implement machines that execute the code of current RISC or CISC instruction set architectures in a VLIW fashion, with backward code compatibility.

Alberto Ferreira de Souza, Peter Rounce

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Backward Code Compatibility | HPCN 1998 | HPCN 1999 | Instruction Set Architectures | Trace Scheduled Vliw |

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Added	05 Aug 2010
Updated	05 Aug 2010
Type	Conference
Year	1998
Where	HPCN
Authors	Alberto Ferreira de Souza, Peter Rounce

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