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2008
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Efficiency and scalability of barrier synchronization on NoC based many-core architectures

11 years 1 months ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip. A fundamental role in highly parallelized applications running on many-core architectures will be played by barrier primitives used to synchronize the execution of parallel processes. This paper focuses on the analysis of the efficiency and scalability of different barrier implementations in manycore architectures based on NoCs. Several message passing barrier implementations based on four algorithms (all-to-all, master-slave, butterfly and tree) have been implemented and evaluated for a single-chip target architecture composed of a variable number of cores (from 4 to 128) and different network topologies (mesh, torus, ring, clustered-ring and fattree). Using a cycle-accurate simulator, we show the scalability of each barrier for every NoC topology, analyzing and comparing theoretical with real behaviors. W...
Oreste Villa, Gianluca Palermo, Cristina Silvano
Added 12 Oct 2010
Updated 12 Oct 2010
Type Conference
Year 2008
Where CASES
Authors Oreste Villa, Gianluca Palermo, Cristina Silvano
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