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TVLSI
2008

Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs

8 years 5 months ago
Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs
Abstract--A distributed on-chip decoupling capacitor network is proposed in this paper. A system of distributed on-chip decoupling capacitors is shown to provide an efficient solution for providing the required on-chip decoupling capacitance under existing technology constraints. In a system of distributed on-chip decoupling capacitors, each capacitor is sized based on the parasitic impedance of the power distribution grid. Various tradeoffs in a system of distributed on-chip decoupling capacitors are also discussed. Related simulation results for typical values of on-chip parasitic resistance are also presented. The worst case error is 0.003% as compared to SPICE.
Mikhail Popovich, Eby G. Friedman, Radu M. Secarea
Added 16 Dec 2010
Updated 16 Dec 2010
Type Journal
Year 2008
Where TVLSI
Authors Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin
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