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2004
IEEE

Efficient exploration of on-chip bus architectures and memory allocation

9 years 2 months ago
Efficient exploration of on-chip bus architectures and memory allocation
Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and mapping. In this paper we present an iterative two-step exploration methodology for bus-based on-chip communication architecture and memory allocation, assuming that memory traces from the processing elements are given from the mapping stage. The proposed method uses a static performance estimation technique to reduce the large design space drastically and quickly, and applies a trace-driven simulation technique to the reduced set of design candidates for accurate performance estimation. Since local memory traffic as well as shared memory traffic are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. The viability and efficiency of the proposed methodology are validated by two reallife examples, 4-channel digital video recorder (DVR) and an equa...
Sungchan Kim, Chaeseok Im, Soonhoi Ha
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2004
Where CODES
Authors Sungchan Kim, Chaeseok Im, Soonhoi Ha
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