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JSA
2007

Efficient FPGA hardware development: A multi-language approach

8 years 8 months ago
Efficient FPGA hardware development: A multi-language approach
This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high level hardware design and efficient hardware implementation. The central idea of this framework is the integration of different hardware languages in a way that harnesses the best features of each language. This is illustrated in this paper by the integration of two hardware languages in the form of HIDE: a structured hardware language ovides more abstract and elegant hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL or Verilog, and Handel-C: an ANSI C-like hardware language which allows software and hardware engineers alike to target FPGAs from high level algorithmic descriptions. On the one hand, HIDE has proven to be very successful in the description and generation of highly optimised parameterisable FPGA circuits from geometric descriptions. On the other hand, Handel-C has also proven to be...
Khaled Benkrid, Abdsamad Benkrid, S. Belkacemi
Added 16 Dec 2010
Updated 16 Dec 2010
Type Journal
Year 2007
Where JSA
Authors Khaled Benkrid, Abdsamad Benkrid, S. Belkacemi
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