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2008
IEEE

An Efficient Hardware Implementation of the Tate Pairing in Characteristic Three

9 years 10 months ago
An Efficient Hardware Implementation of the Tate Pairing in Characteristic Three
DL systems with bilinear structure recently became an important base for cryptographic protocols such as identity-based encryption (IBE). Since the main computational task is the evaluation of the bilinear pairings over elliptic curves, known to be prohibitively expensive, efficient implementations are required to render them applicable in real life scenarios. We present an efficient accelerator for computing the Tate Pairing in characteristic 3, using the ModifiedDuursma-Lee algorithm. Our accelerator shows that it is possible to improve the area-time product by 12 times on FPGA, compared to estimated values from one of the best known hardware architecture [6] implemented on the same type of FPGA. Also the computation time is improved upto 16 times compared to software applications reported in [17]. In addition, we present the result of an ASIC implementation of the algorithm, which is the first hitherto.
Giray Kömürcü, Erkay Savas
Added 30 May 2010
Updated 30 May 2010
Type Conference
Year 2008
Where ICONS
Authors Giray Kömürcü, Erkay Savas
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