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2010
IEEE

Efficient hardware support for the Partitioned Global Address Space

8 years 8 months ago
Efficient hardware support for the Partitioned Global Address Space
We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory. Remote memory access is possible by forwarding local load or store transactions to remote nodes. No software layers are involved in a remote access, neither on origin or target side: a user level process can directly access remote locations without any kind of software involvement. We have implemented the architecture as an FPGA-based prototype in order to demonstrate the functionality of the complete system. This prototype also allows real world measurements in order to show the performance potential of this architecture, in particular for fine grain memory accesses like they are typically used for synchronization tasks. Keywords- computer communications, high performance networking, distributed shared memory
Holger Fröning, Heiner Litz
Added 05 Mar 2011
Updated 05 Mar 2011
Type Journal
Year 2010
Where IPPS
Authors Holger Fröning, Heiner Litz
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