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2007
Springer

Efficient Modeling and Floorplanning of Embedded-FPGA Fabric

10 years 9 months ago
Efficient Modeling and Floorplanning of Embedded-FPGA Fabric
In this paper we present an automatic design flow for generating customized embedded FPGA (eFPGA) fabric and a domain specific SOC+eFPGA architecture. This design flow encompasses both the eFPGA user and automatic layout generator perspectives. We discuss generic FPGA modeling based on VPR, simulation and high-level models of reconfigurable components, and we present an innovative floor-planing for island style FPGAs using rectilinear macros. Several system integration issues are highlighted. Layout of a real life SOC with an embedded RTR FPGA for cryptographic applications, designed with this flow, is also presented.
Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guille
Added 07 Jun 2010
Updated 07 Jun 2010
Type Conference
Year 2007
Where FPL
Authors Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley
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