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2004
IEEE

Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures

9 years 5 months ago
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures
The increasing complexity of system-on-chip (SOC) integrated circuits has spurred the development of versatile automatic test equipment (ATE) that can simultaneously drive different channels at different data rates. Examples of such ATEs include the Agilent 93000 series tester based on port scalability and the test processor-per-pin architecture, and the Tiger system from Teradyne. The number of tester channels with high data rates may be constrained in practice however due to ATE resource limitations, the power rating of the SOC, and scan frequency limits for the embedded cores. Therefore, we formulate the following optimization problem: given two available data rates for the tester channels, an SOC-level test access mechanism (TAM) width
Anuja Sehgal, Krishnendu Chakrabarty
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2004
Where DATE
Authors Anuja Sehgal, Krishnendu Chakrabarty
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