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2008
IEEE

An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA

9 years 4 months ago
An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA
We propose a method to efficiently design a “parity generator”, which is a stand-alone block producing multiple parity bits of a given circuit. The parity generator is designed by duplicating the original circuit, XOR-ing given groups of its outputs and resynthesizing the whole circuit. The resulting circuitry is mostly smaller than the original circuit. The major task to be solved is to properly select the groups of outputs to be XORed to obtain multiple parity bits and maximally reduce the generator size. A method based on principles of the FC-Min minimizer is proposed in this paper. The parity generator is exploited in on-line diagnostics, to design self-checking circuits based on a modified duplex system.
Petr Fiser, Pavel Kubalík, Hana Kubatova
Added 29 May 2010
Updated 29 May 2010
Type Conference
Year 2008
Where DSD
Authors Petr Fiser, Pavel Kubalík, Hana Kubatova
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