Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques

Practical approaches for on-chip inductance extraction to obtain a sparse, stable and accurate inverse inductance matrix K are proposed. The novelty of our work is in using circuit characteristics to define the concept of resistance-dominant and inductancedominant lines. This notion is used to progressively refine a set of clusters that are inductively tightly-coupled. For reasonable designs, the more exact Algorithm 1 yields a sparsification of 97% for delay and oscillation magnitude errors of 10% and 15%, respectively, while the more approximate Algorithm 2 achieves up to 99% sparsification. An offshoot of this work is K-PRIMA, an extension of PRIMA to handle K matrices with guaranteed passivity.

• Type: Conference
• Year: 2002
• Where: ICCD
• Authors: Haitian Hu, Sachin S. Sapatnekar
• Keywords: Accurate Inverse Inductance, Hardware, ICCD 2002, On-chip Inductance Extraction, Oscillation Magnitude Errors