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DAC
2010
ACM

An efficient phase detector connection structure for the skew synchronization system

9 years 5 months ago
An efficient phase detector connection structure for the skew synchronization system
Clock skew optimization continues to be an important concern in circuit designs. To overcome the influence caused by PVT variations, the automatic skew synchronization scheme can dynamically adjust and reduce the clock skew after a chip is manufactured. There are two key components in the skew synchronization scheme: Adjustable Delay Buffer (ADB) and Phase Detector (PD). Most previous researchers have emphasized on ADB placement issues. In this paper, we show that the connection between FFs and PDs can also greatly influence the final clock skew due to the insertion of the PDs. We first analyze the influence of PD connection structures. Then we propose an algorithm to generate a PD connection structure which achieves the minimum influence to the clock skew. Our experimental results are very encouraging. Categories and Subject Descriptors J.6 [COMPUTER-AIDED ENGINEERING]: Computeraided Design (CAD). General Terms Algorithms, Design, Reliability. Keywords Post-Silicon Tuning, Adjustable...
Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih
Added 15 Aug 2010
Updated 15 Aug 2010
Type Conference
Year 2010
Where DAC
Authors Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih-Chieh Chang
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