Efficient pipelining for modular multiplication architectures in prime fields

This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation of the Montgomery algorithm, a more compact pipelined version is derived. The design makes use of 16bit integer multiplication blocks that are available on recently manufactured FPGAs. The critical path is optimized by omitting the exact computation of intermediate results in the Montgomery algorithm using a 6-2 carry-save notation. This results in a high-speed architecture, which outperforms previously designed Montgomery multipliers. Because a very popular application of Montgomery multiplication is public key cryptography, we compare our implementation to the state-of-the-art in Montgomery multipliers on the basis of performance results for 1024-bit RSA. Categories and Subject Descriptors B.2 [Arithmetic and Logic Structures]: High-Speed Arithmetic--Cost/performance; E.3 [Data]: Data Encryption-Public key c...

• Type: Conference
• Year: 2007
• Where: GLVLSI
• Authors: Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid Verbauwhede
• Keywords: GLVLSI 2007, Montgomery Algorithm, Montgomery Multipliers, Public Key Coprocessor, VLSI