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ISQED
2009
IEEE

Efficient statistical analysis of read timing failures in SRAM circuits

10 years 11 months ago
Efficient statistical analysis of read timing failures in SRAM circuits
A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. Unlike existing approaches that focus on cell-level performance metrics for isolated sub-components or ignore inter-die variability, the system-level performance is accurately predicted for the entire SRAM circuit that is impractical to analyze statistically via transistor-level Monte Carlo simulations. The accurate bounding of read timing failures using this methodology is validated with silicon measurements from a 64kb SRAM testchip in 90nm CMOS. We demonstrate the efficacy of this methodology for earlystage design exploration to specify redundancy, required sense amp offset, and other circuit choices as a function of memory size. Keywords SRAM, failure analysis, response surface modeling
Soner Yaldiz, Umut Arslan, Xin Li, Larry T. Pilegg
Added 19 May 2010
Updated 19 May 2010
Type Conference
Year 2009
Where ISQED
Authors Soner Yaldiz, Umut Arslan, Xin Li, Larry T. Pileggi
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