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ISPD
1998
ACM

An efficient technique for device and interconnect optimization in deep submicron designs

9 years 8 months ago
An efficient technique for device and interconnect optimization in deep submicron designs
In this paper, we formulate a new class of optimization problem, named the general CH-posynomial program, and reveal the general dominance property. We propose an efcient algorithm based on the extended local re nement operation to compute lower and upper bounds of the exact solution to the general CH-posynomial program. We apply the algorithm to solve the simultaneous transistor and interconnect sizing STIS problem under the table-based device model, and the global interconnect sizing and spacing GISS problem with consideration of the crosstalk capacitance. Experiment results show that our algorithm can handle many device and interconnect modeling issues in deep submicron designs and is very e cient.
Jason Cong, Lei He
Added 05 Aug 2010
Updated 05 Aug 2010
Type Conference
Year 1998
Where ISPD
Authors Jason Cong, Lei He
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