An efficient wakeup design for energy reduction in high-performance superscalar processors

In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex scheduling logic results in the formation of a hot spot on the processor chip. Consequently, the latency and power consumption of the dynamic scheduler are two of the most crucial design issues when developing a high-performance microprocessor. We propose an instruction wakeup scheme that remedies the speed and power issues faced with conventional designs. This is achieved by a new design that separates RAM cells from the match circuits. This separated design is such that the advantages of the CAM and bitmap RAM schemes are retained, while their respective disadvantages are eliminated. Specifically, the proposed design retains the moderate area advantage of the CAM scheme and the low power and low latency advantages of the bit-map RAM scheme. The experimental results show that the proposed design saves power consum...

• Type: Conference
• Year: 2005
• Where: CF
• Authors: Kuo-Su Hsiao, Chung-Ho Chen
• Keywords: Applied Computing, Bit-map Ram Design, CF 2005, Power Consumption, Ram Scheme