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DAC
2008
ACM

ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction

9 years 3 months ago
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
In this paper, we present ELIAD, an efficient lithography aware detailed router to optimize silicon image after optical proximity correction (OPC) in a correct-by-construction manner. We first propose a compact post-OPC litho-metric for a detailed router based on statistical characterization. We characterize the interferences among weak grids filled with one of predefined litho-prone shapes (e.g., jog-corner, via, line-end). Our litho-metric derived from the characterization shows high fidelity to total edge placement error (EPE) in large scale, compared with Calibre-OPC/ORC. As a chip itself is in the largest scale, ELIAD powered by the proposed metric can enhance the overall post-OPC printed silicon image. Experimental results on 65nm industrial circuits show that ELIAD outperforms a ripup/rerouting approach such as RADAR [17] with 8x more EPE hotspot reduction and 12x speedup. Also, compared with a conventional detailed router, ELIAD is only about 50% slower. Categories and Subject...
Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan
Added 12 Nov 2009
Updated 12 Nov 2009
Type Conference
Year 2008
Where DAC
Authors Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan
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