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ISLPED
2004
ACM

Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization

12 years 5 months ago
Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations that stress the power-delivery network. Recent research has focused on hardware-only mechanisms to detect and eliminate these fluctuations. While the solutions have been effective at avoiding operating-range violations, they have done so at a performance penalty to the executing program. Compilers are well equipped to rearrange instructions such that current fluctuations are less dramatic, with minimal performance implications. Furthermore, a dynamic optimizer can eliminate the problem at run time, avoiding the difficult task of statically predicting voltage emergencies. This paper proposes complementing existing hardware solutions with additional run-time software to address problematic code sequences that cause recurring voltage swings. Our proposal extends existing hardware techniques to additionally prov...
Kim M. Hazelwood, David Brooks
Added 30 Jun 2010
Updated 30 Jun 2010
Type Conference
Year 2004
Where ISLPED
Authors Kim M. Hazelwood, David Brooks
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