Embedded Support Vector Machine : Architectural Enhancements and Evaluation

In recent years, research and development in the field of machine learning and classification techniques have gained paramount importance. The future generation of intelligent embedded devices will obviously require such classifiers working on-line and performing classification tasks in a variety of fields ranging from data mining to recognition tasks in image and video. Among different such techniques, Support Vector Machines (SVMs) have been found to deliver state of the art performance thus emerging as the clear winner. In this work, the Support Vector Machine Learning and Classification tasks are evaluated on embedded processor architectures and subsequent architectural modifications are proposed for performance improvement of the same.

• Type: Conference
• Year: 2007
• Where: VLSID
• Authors: Soumyajit Dey, Monu Kedia, Niket Agarwal, Anupam Basu
• Keywords: Classification Tasks, Computer Architecture, Machine Learning, Support Vector Machine, VLSID 2007