Energy-efficient redundant execution for chip multiprocessors

Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm significantly reduces the energy overhead of redundant execution without sacrificing performance. Our evaluation shows that this architecture has a

• Type: Conference
• Year: 2010
• Where: GLVLSI
• Authors: Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
• Keywords: Future Chip Microprocessors, GLVLSI 2010, On-chip Fault Tolerance, Redundant Execution, VLSI