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GLVLSI
2010
IEEE

Energy-efficient redundant execution for chip multiprocessors

10 years 8 hour ago
Energy-efficient redundant execution for chip multiprocessors
Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm significantly reduces the energy overhead of redundant execution without sacrificing performance. Our evaluation shows that this architecture has a
Pramod Subramanyan, Virendra Singh, Kewal K. Saluj
Added 07 Dec 2010
Updated 07 Dec 2010
Type Conference
Year 2010
Where GLVLSI
Authors Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
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