Energy recovery clocked dynamic logic

Energy recovery clocking results in significant energy savings in clock distribution networks as compared to conventional squarewave clocking. However, since energy recovery clocks are sinusoidal in nature, standard dynamic logic styles do not work efficiently when used with energy recovery clocks. We propose novel dynamic logic styles that operate more efficiently with sinusoidal clocks, enabling energy recovery from their clock networks, and resulting in significant energy savings. Based on the simulation results using TSMC 0.25µm CMOS process technology, at iso-performance, the proposed dynamic logic styles exhibit up to 53% power reduction. Categories and Subject Descriptors B.6.1 [Logic Design]: Design Styles – energy recovery clock, domino logic. General Terms: Performance, Design, Theory.

• Type: Conference
• Year: 2005
• Where: GLVLSI
• Authors: Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy
• Keywords: Dynamic Logic Styles, Energy Recovery, Energy Recovery Clock, GLVLSI 2005, VLSI