Enhanced Architectural Support for Variable-Length Decoding

This paper proposes a new architecture for efficient variable-length decoding (VLD) of entropy-coded data for multimedia applications on general-purpose processors. It improves on earlier proposals for low-complexity performance-enhancing hardware structures that exploit prefix/suffix properties of variable-length codes for common multimedia formats [1]. The enhanced architecture is compared to the previous architectures in terms of complexity and operating speed for FPGA implementation, and also in terms of area requirements, power consumption, and operating speed for a 0.18-µm ASIC fabrication process. Simulation results are reported for a pipelined processor with caches executing MPEG-4 software where VLD performance is doubled by incorporating the proposed architecture.

• Type: Conference
• Year: 2006
• Where: ICMCS
• Authors: Mohanarajah Sinnathamby, Subramania Sudharsanan, Naraig Manjikian
• Keywords: Caches Executing Mpeg-4, ICMCS 2006, Operating Speed, Performance-enhancing Hardware Structures