Equivalent Semantic Translation from Parallel DEVS Models to Time Automata

Dynamic reconfigurable simulation based on Discrete Event System Specification (DEVS) requires efficient verification of simulation models. Traditional verification method of DEVS model is based on I/O test in which a DEVS model is regarded as a black box or a grey box. This method is low efficient and insufficient because input samples are often limited. This paper proposes a formal method which can translate Parallel DEVS model into a restrict kind of Timed Automata (TA) with equivalent behaviors. By this translation, a formal verification problem of Parallel DEVS model can be changed into the formal verification of according timed automata.

• Type: Conference
• Year: 2007
• Where: ICCS
• Authors: Shoupeng Han, Kedi Huang
• Keywords: DEVS Model, Formal Verification, ICCS 2007, Parallel DEVS Model