Sciweavers

Share
MICRO
2010
IEEE

Erasing Core Boundaries for Robust and Configurable Performance

9 years 5 months ago
Erasing Core Boundaries for Robust and Configurable Performance
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address these issues, a more fundamental change to the fabric of multicore systems is necessary to seamlessly combat these challenges. Towards this end, this paper proposes CoreGenesis, a dynamically adaptive multiprocessor fabric that blurs out individual core boundaries, and encourages resource sharing across cores for performance, fault tolerance and customized processing. Further, as a manifestation of this vision, the paper provides details of a unified performance-reliability solution that can assemble variable-width processors from a network of (potentially broken) pipeline stage-level resources. This design relies on interconnection flexibility, microarchitectural innovations, and compiler directed instruction steering, to merge pipeline resources for high single-thread performance. The same flexibility enables i...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott
Added 14 Feb 2011
Updated 14 Feb 2011
Type Journal
Year 2010
Where MICRO
Authors Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott A. Mahlke
Comments (0)
books