Error Containment in the Time-Triggered System-On-a-Chip Architecture

Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports the integration of multiple application subsystems of different criticality levels within a single hardware platform. A pivotal property of the architecture is the integrated error containment, which facilitates modular certification, robustness, and composability. By dividing the complete SoC into physically separated components that interact exclusively by the timely exchange of messages on a timetriggered Network-on-a-Chip (NoC), we achieve error containment for both computational and communication resources. The time-triggered design allows protecting the access to the NoC with guardians that are associated with each component. Based on the protection of the time-triggered NoC with inherent predictability and determinism, the architecture also enables error containment for faulty computational results. T...

• Type: Conference
• Year: 2007
• Where: IESS
• Authors: Roman Obermaisser, Hermann Kopetz, Christian El Salloum, Bernhard Huber
• Keywords: Embedded Systems, Error Containment, Error Containment Mechanisms, IESS 2007, Integrated Error Containment