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WMPI
2004
ACM

Evaluating kilo-instruction multiprocessors

13 years 9 months ago
Evaluating kilo-instruction multiprocessors
The ever increasing gap in processor and memory speeds has a very negative impact on performance. One possible solution to overcome this problem is the Kilo-instruction processor. It is a recent proposed architecture able to hide large memory latencies by having thousands of in-flight instructions. Current multiprocessor systems also have to deal with this increasing memory latency while facing other sources of latencies: those coming from communication among processors. What we propose, in this paper, is the use of Kilo-instruction processors as computing nodes for small-scale CC-NUMA multiprocessors. We evaluate what we appropriately call Kilo-instruction Multiprocessors. This kind of systems appears to achieve very good performance while showing two interesting behaviours. First, the great amount of in-flight instructions makes the system not just to hide the latencies coming from the memory accesses but also the inherent communication latencies involved in remote memory accesses....
Marco Galluzzi, Ramón Beivide, Valentin Pue
Added 30 Jun 2010
Updated 30 Jun 2010
Type Conference
Year 2004
Where WMPI
Authors Marco Galluzzi, Ramón Beivide, Valentin Puente, José-Ángel Gregorio, Adrián Cristal, Mateo Valero
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