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SAMOS
2007
Springer

Evaluating Large System-on-Chip on Multi-FPGA Platform

9 years 4 months ago
Evaluating Large System-on-Chip on Multi-FPGA Platform
This paper presents a configurable base architecture tailorable for different applications. It allows simple and rapid way to evaluate and prototype large Multi-Processor System-on-Chip architectures on multiple FPGAs with support to Globally Asynchronous Locally Synchronous scheme. It allows early /software co-verification and optimization. The architecture abstracts the underlying hardware details from the processors so that knowledge about the exact locations of individual components are not required for communication. Implemented example architecture contains 58 IP blocks, including 35 Nios II soft processors. As a proof of concept, a MPEG-4 video encoder is run on the example architecture.
Ari Kulmala, Erno Salminen, Timo D. Hämä
Added 09 Jun 2010
Updated 09 Jun 2010
Type Conference
Year 2007
Where SAMOS
Authors Ari Kulmala, Erno Salminen, Timo D. Hämäläinen
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