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1998
IEEE

Evaluation of a Low-Power Reconfigurable DSP Architecture

9 years 4 months ago
Evaluation of a Low-Power Reconfigurable DSP Architecture
Abstract. Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an architecture that relies on dynamic reconfiguration of hardware resources to implement low-power and programmable processors for DSP applications. In this paper, we evaluate this architectural approach and compare it to other programmable architectures.
Arthur Abnous, Katsunori Seno, Yuji Ichikawa, Marl
Added 05 Aug 2010
Updated 05 Aug 2010
Type Conference
Year 1998
Where IPPS
Authors Arthur Abnous, Katsunori Seno, Yuji Ichikawa, Marlene Wan, Jan M. Rabaey
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