Exciting Stuck-Open faults in CMOS Circuits Using ILP Techniques

To excite a stuck-open fault in a CMOS combinational circuit, it is only necessary that the output of the gate containing the fault takes on opposite values during the application of two successive input vectors to the primary inputs of the circuit. In this paper we formulate the excitation problem as an ILP instance and use two advanced ILP solvers, one is Boolean satisfiability (SAT)-based and the other is generic, to search for a pair of input vectors that maximizes the simultaneous excitation of as many stuck-open faults in the circuit as possible. The proposed approach was tested using benchmarks from the ISCAS 89 suite of circuits. Experimental results indicate that fault-excitation, within a reasonable CPU time limit, is possible in most cases.

• Type: Conference
• Year: 2006
• Where: AICCSA
• Authors: Fadi A. Aloul, Assim Sagahyroon, Bashar Al Rawi
• Keywords: AICCSA 2006, CMOS Combinational Circuit, Hardware, Input Vectors, Stuck-open Faults