Experiences with Soft-Core Processor Design

Soft-core processors exploit the flexibility of Field Programmable Gate Arrays (FPGAs) to allow a system designer to customize the processor to the needs of a target application. This paper describes the UT Nios implementation of Altera’s Nios architecture. A benchmark set appropriate for soft-core processors is defined. Using the benchmark set, the performance of UT Nios is explored and compared with the commercial implementation.

• Type: Conference
• Year: 2005
• Where: IPPS
• Authors: Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown
• Keywords: Altera’s Nios Architecture, Distributed And Parallel Computing, IPPS 2005, UT Nios, UT Nios Implementation