Sciweavers

Share
IPPS
2005
IEEE

Experiences with Soft-Core Processor Design

9 years 4 months ago
Experiences with Soft-Core Processor Design
Soft-core processors exploit the flexibility of Field Programmable Gate Arrays (FPGAs) to allow a system designer to customize the processor to the needs of a target application. This paper describes the UT Nios implementation of Altera’s Nios architecture. A benchmark set appropriate for soft-core processors is defined. Using the benchmark set, the performance of UT Nios is explored and compared with the commercial implementation.
Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Ste
Added 25 Jun 2010
Updated 25 Jun 2010
Type Conference
Year 2005
Where IPPS
Authors Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown
Comments (0)
books