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2003
ACM

Exploiting compiler-generated schedules for energy savings in high-performance processors

11 years 5 months ago
Exploiting compiler-generated schedules for energy savings in high-performance processors
This paper develops a technique that uniquely combines the advantages of static scheduling and dynamic scheduling to reduce the energy consumed in modern superscalar processors with out-of-order issue logic. In this HybridScheduling paradigm, regions of the application containing large amounts of parallelism visible at compile-time completely bypass the dynamic scheduling logic and execute in a low power static mode. Simulation studies using the Wattch framework on several media and scientific benchmarks demonstrate large improvements in overall energy consumption of 43% in kernels and 25% in full applications with only a 2.8% performance degradation on average. Categories and Subject Descriptors C.1 [Processor Architectures]: RISC/CISC, VLIW Architectures General Terms Performance, Design Keywords Low Energy, Instruction-Level Parallelism, Dynamic Issue Processors, Very Long Instruction Word Architectures
Madhavi Gopal Valluri, Lizy Kurian John, Heather H
Added 05 Jul 2010
Updated 05 Jul 2010
Type Conference
Year 2003
Where ISLPED
Authors Madhavi Gopal Valluri, Lizy Kurian John, Heather Hanson
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