Exploiting Dual Data-Memory Banks in Digital Signal Processors

Over the past decade, digital signal processors (DSPs) have emerged as the processors of choice for implementing embedded applications in high-volume consumer products. Through their use of specialized hardware features and small chip areas, DSPs provide the high performance necessary for embedded applications at the low costs demanded by the high-volume consumer market. One feature commonly found in DSPs is the use of dual data-memory banks to double the memory system's bandwidth. When coupled with high-order data interleaving, dual memory banks provide the same bandwidth as more costly memory organizations such as a dual-ported memory. However, making effective use of dual memory banks remains difficult, especially for high-level language (HLL) DSP compilers. In this paper, we describe two algorithms

• Type: Conference
• Year: 1996
• Where: ASPLOS
• Authors: Mazen A. R. Saghir, Paul Chow, Corinna G. Lee
• Keywords: ASPLOS 1996, Dual Data-memory Banks, Dual Memory Banks, Partial Data Duplication, Programming Languages