Sciweavers

Share
ISCA
1998
IEEE

Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor

11 years 11 months ago
Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor
Much of the improvement in computer performance over the last twenty years has come from faster transistors and architectural advances that increase parallelism. Historically, parallelism has been exploited either at the instruction level with a grain-size of a single instruction or by partitioning applications into coarse threads with grain-sizes of thousands of instructions. Fine
Stephen W. Keckler, William J. Dally, Daniel Maski
Added 05 Aug 2010
Updated 05 Aug 2010
Type Conference
Year 1998
Where ISCA
Authors Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, Whay Sing Lee
Comments (0)
books