Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor

Much of the improvement in computer performance over the last twenty years has come from faster transistors and architectural advances that increase parallelism. Historically, parallelism has been exploited either at the instruction level with a grain-size of a single instruction or by partitioning applications into coarse threads with grain-sizes of thousands of instructions. Fine

• Type: Conference
• Year: 1998
• Where: ISCA
• Authors: Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, Whay Sing Lee
• Keywords: Coarse Threads, Faster Transistors, Hardware, ISCA 1998, Times Faster Communication