Exploiting pipelining to relax register-file port constraints of instruction-set extensions

Customisable embedded processors are becoming available on the market, thus making it possible for designers to speed up execution of applications by using Application-specific Functional Units (AFUs), implementing Instruction-Set Extensions (ISEs). While these processors have become available, the state of the art on automatic ISE identification is improving; many algorithms are being proposed for choosing, given the application’s source code, the best ISEs under various constraints. Read and write ports between the AFUs and the processor register file are an expensive asset, fixed in the microarchitecture—some processors indeed only allow two read and one write ports—and, on the other hand, a large availability of inputs and outputs to and from the AFUs exposes high speedup. This paper proposes a solution to the limitation of actual register file ports by serialising register file access and therefore addressing multi-cycle read and write. It does so in an innovative way...

• Type: Conference
• Year: 2005
• Where: CASES
• Authors: Laura Pozzi, Paolo Ienne
• Keywords: CASES 2005, ISE Identification, Register file, Register file Access, System Software