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ICCD
2004
IEEE

Exploiting Quiescent States in Register Lifetime

14 years 16 days ago
Exploiting Quiescent States in Register Lifetime
Large register file with multiple ports, but with a minimal access time, is a critical component in a superscalar processor. Analysis of the lifetime of a logical to physical register mapping reveals that there are long latencies between the times a physical register is allocated, consumed, and released. In this paper, we propose a TriBank register file, a novel register file organization that exploits such long latencies, resulting in a larger register bandwidth and a smaller register access time. Implementation of the TriBank register file organization, as compared to a conventional monolithic register file in an 8-wide out-of-order issue superscalar processor reduced the register access time up to 34%, even while enhancing the throughput in instructions per cycle (IPC) by 3% and 14%, for SpecInt2000 and SpecFP2000, respectively.
Rama Sangireddy, Arun K. Somani
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2004
Where ICCD
Authors Rama Sangireddy, Arun K. Somani
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