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ASPDAC
2008
ACM

Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching

10 years 6 months ago
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it also degrades robustness. Recently, researchers have proposed novel design technique for linear time complexity adders that maintain high yield and high clock frequency even at scaled supply voltage. The idea is based on the fact that the critical paths of arithmetic units are exercised rarely. The technique (a) predicts the set of critical paths, (b) reduces the supply voltage to operate non-critical paths at rated frequency, and; (c) avoids possible delay failures in the critical paths by dynamically stretching the clock period (to say, two-cycles assuming all standard operations are single-cycle), when they are activated. This allows circuits to operate at scaled supply with minimal performance degradation. The off-critical paths operate in single clock cycle while critical paths are operated in stretched cl...
Swaroop Ghosh, Kaushik Roy
Added 12 Oct 2010
Updated 12 Oct 2010
Type Conference
Year 2008
Where ASPDAC
Authors Swaroop Ghosh, Kaushik Roy
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