An extension to JTAG for at-speed debug on a system

When developing new designs, debugging the prototype is important to resolve application malfunction. During this board design debug, often a few pins of an IC are measured to check signals. Access to these pins is becoming more difficult due to packages like BGA. The JTAG port is an efficient mechanism to gain more access to the ICs. A method is presented to reconfigure the boundary scan chain to any desired length and to access pins involved in the debugging. The method is used asynchronously or synchronously to the test clock. In asynchronous mode high transfer frequencies are possible. For synchronous mode two different variants are described where the data throughput is determined by the intermediate logic. Both modes have proven to work on an FPGA and all implementations fully retain compliancy to the IEEE1149.1 standard.

• Type: Conference
• Year: 2003
• Where: ITC
• Authors: Leon van de Logt, Frank van der Heyden, Tom Waayers
• Keywords: Board Design Debug, Boundary Scan Chain, Hardware, ITC 2003, Pins