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DAC
2002
ACM

False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

12 years 9 months ago
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation
We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool can characterize statistical circuit delay distribution for the entire circuit and produce a set of true critical paths. Categories and Subject Descriptors B.8.2 [Hardware]: Performance Analysis and Design Aids General Terms Algorithm, Performance, Reliability Keywords Critical path selection, false path, statistical timing analysis
Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ti
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2002
Where DAC
Authors Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ting Cheng
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